Silicon is the most prevalent material in electronics, no matter whether for mobile phones, solar cells or computers. Nanometer-sized wires made of silicon have a large potential for a completely new chip architecture. But this requires a detailed investigation and understanding of their electronic properties which is technologically challenging due to the ultra-small size of the nanowires. Researchers from the Max Planck Institute of Microstructure Physics and the Forschungszentrum Dresden-Rossendorf (FZD) were able to describe the electrical resistance and current flow inside individual silicon nanowires. The results were published in the journal NANO LETTERS.
Pressemitteilung vom 18.01.2010: Hoch statt flach: Nanodrähte für eine neue Chip-Architektur, FZD und Max-Planck-Institut für Mikrostrukturphysik, Publikation in Nano Letters

3D scheme of a usual transistor (left) and of a novel vertical transistor made out of silicon. The arrows symbolize the current flow.

All pictures: Sander Münster, Dresden.

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Nowadays, a myriad of silicon transistors are responsible to pass on the information on a microchip. The transistors are arranged in a planar array, i.e. lying flat next to each other, and have shrunk down already to a size of only about 50 nanometers (1 nanometer = 1 millionth part of 1 millimeter). Further miniaturization of transistors with a planar structure will soon come to an end due to fundamental physical limits. Still, even smaller transistors are desirable in order to continuously improve their functions while reducing the cost of the electronics.

Currently, researchers are working hard to find new approaches to overcome the physical limits on downscaling and integration of microchips. One such concept is to fabricate a completely new transistor architecture in three-dimensions. In this concept, instead of arranging them flat on the substrate the silicon transistors are turned by 90 degrees so that they stick out of the chip substrate like tiny columns. In this way, numerous vertical transistors could be built on the area normally occupied by only one planar transistor.